VHDL CODE OF ADDER /SUBTRACTOR

VHDL CODE OF ADDER /SUBTRACTOR

an adder/subtractor circuit ,as the name indicates ,is able to perform addition as well as subtraction.Here ,I used 4 bit addition and subtraction units together.(Such a circuit is available in the market. It is 7483).Here ,I have a control signal as input ,in addition to the conventional inputs.Here,when the control signal is '0' addition takes place.When control signal is '1',subtraction takes place.The control signal is represented as ADD_SB.Now consider the logic diagram shown below.If you are not familiar with the design of this circuit,please refer any standard text book of Digital Electronics.



Now consider the VHDL code
--FIRST START WITH A FULL ADDER
--THEN DESIGN XOR GATE
--THEN BIND 4 FULL ADDERS AND 4 XOR GATES
--PURE STRUCTURAL MODELING
--MIXED OR BEHAVIORAL ALSO CAN BE USED
--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
--I AM GOING TO DESIGN AN ENTITY FOR XOR FUNCTION
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_1 IS
PORT(A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);
END XOR_1;
ARCHITECTURE BEHV OF XOR_1 IS
BEGIN
Y<=A XOR B;
END BEHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD_SUB IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);AD_SB:IN STD_LOGIC;SUM_DIF:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT :OUT STD_LOGIC);
END ADD_SUB;
ARCHITECTURE BEH123 OF ADD_SUB IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C_TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
XOR1:ENTITY WORK.XOR_1 PORT MAP(B(0),AD_SB,TEMP(0));
XOR2:ENTITY WORK.XOR_1 PORT MAP(B(1),AD_SB,TEMP(1));
XOR3:ENTITY WORK.XOR_1 PORT MAP (B(2),AD_SB,TEMP(2));
XOR4:ENTITY WORK.XOR_1 PORT MAP (B(3),AD_SB,TEMP(3));
-- INV1:ENTITY WORK.INV PORT MAP (AD_SB,CTRL);
--ADDER:ENTITY WORK.ADDER_4BIT PORT MAP(A,TEMP,SUM,COUT);
FA1:ENTITY WORK.FA PORT MAP (A(0),TEMP(0),AD_SB,SUM_DIF(0),C_TEMP(0));
FA2:ENTITY WORK.FA PORT MAP (A(1),TEMP(1),C_TEMP(0),SUM_DIF(1),C_TEMP(1));
FA3:ENTITY WORK.FA PORT MAP (A(2),TEMP(2),C_TEMP(1),SUM_DIF(2),C_TEMP(2));
FA4:ENTITY WORK.FA PORT MAP (A(3),TEMP(3),C_TEMP(2),SUM_DIF(3),COUT);
END BEH123;

 

VHDL MODEL OF SUBTRACTOR

Subtraction can be implemented by adder.2's complement addition is same as that of subtraction.I already discussed the 4 bit parallel adder,so I am skipping that discussion here.In addition to that circuit,we need a 2's complement conversion of the number to be subtracted.Remember,this is not the easiest way to implement subtraction. If you are familiar with various packages available in VHDL library,you can use it here. This code is to understand structural style of modeling(or the low level modeling principles).

The VHDL code is shown below

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
-- NOW DESIGN A 4 BIT ADDING UNIT BY CASCADING 4 FULL ADDER UNITS
--STRUCTURAL BINDING OF UNITS ENTITY FA 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADDER_4BIT IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);C:OUT STD_LOGIC);
END ADDER_4BIT;
ARCHITECTURE BEHV OF ADDER_4BIT IS
SIGNAL TEMP:STD_LOGIC:='0';
SIGNAL CAR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
FA1:ENTITY WORK.FA PORT MAP(A(0),B(0),TEMP,S(0),CAR(0));
FA2:ENTITY WORK.FA PORT MAP(A(1),B(1),CAR(0),S(1),CAR(1));
FA3:ENTITY WORK.FA PORT MAP(A(2),B(2),CAR(1),S(2),CAR(2));
FA4:ENTITY WORK.FA PORT MAP(A(3),B(3),CAR(2),S(3),C);
END BEHV;

--NOW I AM GOING TO DEVELOP A 4 BIT SUBSTRACTOR 
--2'S COMPLEMENT ADDITION IS USING
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--TO USE "+" FUNCTION 
ENTITY SUB_4BIT IS
PORT(AIN,BIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);DIFF:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);BOR:OUT STD_LOGIC);
END SUB_4BIT;
ARCHITECTURE BEH OF SUB_4BIT IS
SIGNAL TEMP,TEMP1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
TEMP<=NOT BIN;
TEMP1<=TEMP+"0001";
ADDERUNIT:ENTITY WORK.ADDER_4BIT PORT MAP(AIN,TEMP1,DIFF,BOR);
END BEH;