VHDL ---- full adder

FULL ADDER

VHDL code for full adder is generated using three different modeling styles i.e Structural, Data-flow and Algorithmic. Thus three different architectures are written for the same design entity FULL_ADDER.

Structural Description:

In Structural description, Structural architecture of the design entity describes it in terms of interconnected components. Each component may be in turn described as interconnected subcomponents or behavioral in terms of built-in functions.

The first step in writing VHDL code for structural architectures is to write the codes for components in separate design entities and analyze them. Analysis creates simulation files in WORK directory. Using those files in the configuration commands of the design code of parent circuit, allows us to use those design entities as components in our parent circuit.

In the generation of the structural code for Full adder, we will generate VHDL code of all three components i.e XOR, AND and OR gates as shown in the figure 1, in the separate design entities.

CODE


Library ieee;

Use ieee.std_logic_1164.all;



ENTITY fulladder IS

PORT( A,B,Cin : IN std_logic;

sum,Cout: OUT std_logic);

END ENTITY;



ARCHITECTURE functional OF fulladder IS

BEGIN

PROCESS(A,B,Cin)

BEGIN

If (Cin = '0' and A = '0' and B = '0' ) then

sum<= '0'; Cout <= '0';

elsif(Cin = '0' and A = '0' and B = '1') then

sum <= '1' ; Cout <= '0';

elsif(Cin = '0' and A = '1' and B = '0' ) then

sum <= '1' ; Cout <= '0';

elsif(Cin = '0' and A = '1' and B = '1' ) then

sum<= '0'; Cout <= '1';

elsif(Cin = '1' and A = '0' and B = '0' ) then

sum <= '1' ; Cout <= '0';

elsif(Cin = '1' and A = '0' and B = '1' ) then

sum<= '0'; Cout <= '1';

elsif(Cin = '1' and A = '1' and B = '0' ) then

sum<= '0'; Cout <= '1';

elsif(Cin = '1' and A = '1' and B = '1' ) then

sum <= '1' ; Cout <= '1';

else

sum <= 'X' ; Cout <= 'X';

end if;

END PROCESS;

END functional;